Circuit layout structure

ABSTRACT

Main-transistors M 1  and M 2  are divided into sub-transistors that are arrayed in a matrix with four rows and four columns to form four cells so that each of the cells is formed of four of the sub-transistors that have a common center. This can realize a layout configuration that is as good in matching of the main-transistors M 1  and M 2  as a four-segment layout scheme and takes small pattern area.

BACKGROUND OF THE INVENTION

1. Field of the Invention

This invention relates to a circuit layout configuration, for example, acircuit layout configuration to improve matching characteristics of atransistor pair in a circuit having the transistor pair such as acurrent mirror circuit and a differential amplifier.

2. Description of the Related Art

Close matching between the transistors is important for theconfiguration of the current mirror circuit and of the differentialamplifier. In particular, the close matching helps in obtaining a lowoffset operational amplifier. FIG. 7 is a circuit diagram showing adifferential gain stage. A pair of MOS transistors M3 and M4 forms acurrent mirror circuit 10 and another pair of MOS transistors M1 and M2forms a differential input pair 11. Each of the pairs of MOS transistorsrequires close matching respectively.

The most basic layout scheme to implement the current mirror circuit 10is a lateral layout scheme. A better option is a common-centroid layoutscheme. These layout schemes and a scheme called four-segment layoutscheme are described in the following document.

Mao-Feng Lan, Anilkumar Tammineedi and Randall Geiger, “Current MirrorLayout Strategies for Enhancing Matching Performance”, Analog IntegratedCircuits and Signal Processing, vol. 28, PP. 9-26, July 2001.

These conventional layout schemes will be explained hereinafter. FIG. 8shows the common-centroid layout scheme. FIG. 9 shows an equivalentcircuit of FIG. 8. M1 and M2 are MOS field effect transistors that areto be matched. The transistor M1 is divided into two sub-transistorsMS11 and MS12. Similarly, the transistor M2 is divided into twosub-transistors MS21 and MS22.

Since these sub-transistors have a common center P as shown in FIG. 8,it is called the common-centroid layout scheme. And gates, drains andsources of the sub-transistors MS11 and MS12 are connected in common toform the transistor M1, as shown in FIG. 9. Similarly, gates, drains andsources of the sub-transistors MS21 and MS22 are connected in common toform the transistor M2.

And now, when the following document on transistor-matching andprocess-dependent layout structures is referred, transistors in variouslayouts are modeled.

M. J. M. Pelgrom, A. C. J. Duinmaijer and A. P. G. Welbers, “Matchingproperties of MOS transistors” IEEE JSSC, Vol. SC-24, PP. 1433-1439,1989.

According to the document, an equivalent threshold voltage for such adevice is given by the following equation.

$V_{Teq} = \frac{\int_{active}{\int_{area}{{V_{T}\left( {x,y} \right)}\ {\mathbb{d}x}\ {\mathbb{d}y}}}}{ActiveArea}$

Here, the Active Area denotes an active area of the sub-transistor, thatis, a channel region through which a current flows. V_(T)(x, y) is alocal threshold voltage that depends on x and y coordinates. A surfaceintegral of V_(T)(x, y) over the active region is calculated to find itsaverage.

And the threshold voltage varies from place to place on a surface of awafer because of processing. Modeling of the variation in the thresholdvoltage is made possible by introducing a gradient amplitude a and agradient direction θ from an origin O shown in FIG. 8.

Therefore, each of corresponding threshold voltages V_(T11), V_(T12),V_(T21) and V_(T22) can be obtained by applying such a threshold voltagemodel to each of the above mentioned sub-transistors MS11, MS12, MS21and MS22, respectively.

First, the threshold voltage V_(T11) of the sub-transistor MS11 is givenby the following equation.

MS11:  $V_{T11} = \frac{\int_{({L_{S} + d_{2}})}^{({{2L_{S}} + d_{2}})}{\int_{({W_{S} + d_{1}})}^{({{2W_{S}} + d_{1}})}{\begin{bmatrix}{V_{T} + \left( {L_{S}{\alpha sin\theta}} \right) +} \\\left( {W_{S}{\alpha cos\theta}} \right)\end{bmatrix} \times \left\lbrack \ {\mathbb{d}W} \right\rbrack \times \left\lbrack \ {\mathbb{d}L} \right\rbrack}}}{W_{s} \times L_{S}}$$V_{T11} = \frac{\int_{({L_{S} + d_{2}})}^{({{2L_{S}} + d_{2}})}{\begin{bmatrix}{{V_{T}W_{S}} + {L_{S}W_{S}{\alpha sin\theta}} + {\alpha cos\theta}} \\\left( \frac{\ {\left( {d_{1} + {2W_{S}}} \right)^{2} - \left( {d_{1} + W_{S}} \right)^{2}}}{2} \right)\end{bmatrix}\left\lbrack {\mathbb{d}L} \right\rbrack}}{W_{s} \times L_{S}}$$V_{T11} = \frac{\int_{({L_{S} + d_{2}})}^{({{2L_{S}} + d_{2}})}{\begin{bmatrix}{{V_{T}W_{S}} + {L_{S}W_{S}{\alpha sin\theta}} +} \\{{\alpha cos\theta}\left( \frac{\ \begin{matrix}{d_{1}^{2} + {4W_{S}^{2}} + {4d_{1}W_{S}} -} \\{d_{1}^{2} - W_{S}^{2} - {2d_{1}W_{S}}}\end{matrix}}{2} \right)}\end{bmatrix}\left\lbrack {\mathbb{d}L} \right\rbrack}}{W_{s} \times L_{S}}$$V_{T11} = \frac{\int_{({L_{S} + d_{2}})}^{({{2L_{S}} + d_{2}})}{\begin{bmatrix}{{V_{T}W_{S}} + {L_{S}W_{S}{\alpha sin\theta}} + {\alpha cos\theta}} \\\left( \frac{\ {{3W_{S}^{2}} + {2W_{S}d_{1}}}}{2} \right)\end{bmatrix}\left\lbrack {\mathbb{d}L} \right\rbrack}}{W_{S} \times L_{S}}$$V_{T11} = \frac{\int_{({L_{S} + d_{2}})}^{({{2L_{S}} + d_{2}})}{\begin{bmatrix}{V_{T} + {L_{S}{\alpha sin\theta}} +} \\{{\alpha cos\theta}\left( {\frac{\ {3W_{S}}}{2} + d_{1}} \right)}\end{bmatrix}\left\lbrack {\mathbb{d}L} \right\rbrack}}{L_{S}}$$V_{T11} = \frac{\begin{matrix}\left\lbrack {{V_{T}L_{S}} + {{\alpha cos\theta}\mspace{11mu}\left( {\frac{\ {3W_{S}}}{2} + d_{1}} \right)\mspace{11mu} L_{S}} +} \right. \\\left. {{\alpha sin\theta}\mspace{11mu}\left( \frac{\left( {{2L_{S}} + d_{2}} \right)^{2} - \left( {L_{S} + d_{2}} \right)^{2}}{2} \right)} \right\rbrack\end{matrix}}{L_{S}}$ $V_{T11} = \frac{\begin{bmatrix}{{V_{T}L_{S}} + {{\alpha cos\theta}\mspace{11mu}\left( {\frac{\ {3W_{S}}}{2} + d_{1}} \right)\mspace{11mu} L_{S}} +} \\{{\alpha sin\theta}\left( \frac{{4L_{S}^{2}} + d_{2}^{2} + {4L_{S}d_{2}} - L_{S}^{2} - d_{2}^{2} - {2L_{S}d_{2}}}{2} \right)}\end{bmatrix}}{L_{S}}$ $\begin{matrix}{V_{T11} = \frac{\left\lbrack {{V_{T}L_{S}} + {{\alpha cos\theta}\mspace{11mu}\left( {\frac{\ {3W_{S}}}{2} + d_{1}} \right)\mspace{11mu} L_{S}} + {{\alpha sin\theta}\mspace{11mu}\left( \frac{{3L_{S}^{2}} + {2L_{S}d_{2}}}{2} \right)}} \right\rbrack}{L_{S}}} \\{V_{T11} = {V_{T} + {\alpha\mspace{11mu}\left( {\frac{\ {3W_{S}}}{2} + d_{1}} \right)\mspace{11mu}\cos\;\theta} + {\alpha\mspace{11mu}\left( {\frac{3L_{S}}{2} + d_{2}} \right)\mspace{11mu}\sin\;\theta}}}\end{matrix}$

Similarly, the threshold voltage V_(T12) of the sub-transistor MS12 isgiven by the following equation.

${{MS12}\text{:}\mspace{14mu} V_{T12}} = {V_{T} + {\frac{W_{S}}{2}{\alpha cos\theta}} + {\frac{L_{S}}{2}{\alpha sin\theta}}}$

Similarly, the threshold voltage V_(T21) of the sub-transistor MS21 isgiven by the following equation.

${{MS21}\text{:}\mspace{14mu} V_{T21}} = {V_{T} + {\alpha\mspace{11mu}\left( {\frac{3W_{S}}{2} + d_{1}} \right)\mspace{11mu}\cos\;\theta} + {\frac{L_{S}}{2}{\alpha sin\theta}}}$

Similarly, the threshold voltage V_(T22) of the sub-transistor MS22 isgiven by the following equation.

${{MS22}\text{:}\mspace{14mu} V_{T22}} = {V_{T} + {\frac{W_{S}}{2}{\alpha cos\theta}} + {\alpha\mspace{14mu}\left( {\frac{3L_{S}}{2} + d_{2}} \right)\mspace{14mu}\sin\;\theta}}$

In the equations described above, d1 denotes a distance between drains(sources) of neighboring sub-transistors, d2 denotes a distance betweengates of neighboring sub-transistors, Ws denotes a width of the gate ofthe sub-transistor and Ls denotes a length of the gate of thesub-transistor.

Next, FIG. 10 shows the four-segment layout scheme. FIG. 11 shows anequivalent circuit of FIG. 10. M1 and M2 are MOS field effecttransistors that are to be matched. The transistor M1 is divided intofour sub-transistors MS11, MS12, MS13 and MS14. These sub-transistorsare disposed in four segments.

Similarly, the transistor M2 is divided into four sub-transistors MS21,MS22, MS23 and MS24. These sub-transistors are disposed in foursegments.

An origin O, a gradient amplitude a and a gradient direction θ are alsodefined with respect to the four-segment layout scheme as shown in FIG.10, and equations below that describe results of the modeling of thethreshold values are obtained. That is, it is assumed in the followingequations that a threshold value of the sub-transistor MS11 is V_(T11),a threshold value of the sub-transistor MS12 is V_(T12), a thresholdvalue of the sub-transistor MS13 is V_(T13), a threshold value of thesub-transistor MS14 is V_(T14), a threshold value of the sub-transistorMS21 is V_(T21), a threshold value of the sub-transistor MS22 isV_(T22), a threshold value of the sub-transistor MS23 is V_(T23) and athreshold value of the sub-transistor MS24 is V_(T24).

${{MS11}\text{:}\mspace{14mu} V_{T11}} = {V_{T} - {{\alpha\left( {\frac{W}{2} + \frac{d_{1}}{2}} \right)}\mspace{11mu}\cos\;\theta} + {\alpha\mspace{11mu}\left( {\frac{L}{2} + W + \frac{3d_{1}}{2}} \right)\mspace{11mu}\sin\;\theta}}$${{MS12}\text{:}\mspace{14mu} V_{T12}} = {V_{T} + {{\alpha\left( {W + \frac{L}{2} + \frac{3d_{1}}{2}} \right)}\mspace{11mu}\cos\;\theta} + {\alpha\mspace{11mu}\left( {\frac{W}{2} + \frac{d_{1}}{2}} \right)\mspace{11mu}\sin\;\theta}}$${{MS13}\text{:}\mspace{14mu} V_{T13}} = {V_{T} + {{\alpha\left( {\frac{W}{2} + \frac{d_{1}}{2}} \right)}\mspace{11mu}\cos\;\theta} - {\alpha\mspace{11mu}\left( {\frac{L}{2} + W + \frac{3d_{1}}{2}} \right)\mspace{11mu}\sin\;\theta}}$${{MS14}\text{:}\mspace{14mu} V_{T14}} = {V_{T} - {{\alpha\left( {W + \frac{L}{2} + \frac{3d_{1}}{2}} \right)}\mspace{11mu}\cos\;\theta} - {\alpha\mspace{11mu}\left( {\frac{W}{2} + \frac{d_{1}}{2}} \right)\mspace{11mu}\sin\;\theta}}$${{MS21}\text{:}\mspace{14mu} V_{T21}} = {V_{T} + {{\alpha\left( {\frac{W}{2} + \frac{d_{1}}{2}} \right)}\mspace{11mu}\cos\;\theta} + {\alpha\mspace{11mu}\left( {\frac{L}{2} + W + \frac{3d_{1}}{2}} \right)\mspace{11mu}\sin\;\theta}}$${{MS22}\text{:}\mspace{14mu} V_{T22}} = {V_{T} + {{\alpha\left( {W + \frac{L}{2} + \frac{3d_{1}}{2}} \right)}\mspace{11mu}\cos\;\theta} - {\alpha\mspace{11mu}\left( {\frac{W}{2} + \frac{d_{1}}{2}} \right)\mspace{11mu}\sin\;\theta}}$${{MS23}\text{:}\mspace{14mu} V_{T23}} = {V_{T} - {{\alpha\left( {\frac{W}{2} + \frac{d_{1}}{2}} \right)}\mspace{11mu}\cos\;\theta} - {\alpha\mspace{11mu}\left( {\frac{L}{2} + W + \frac{3d_{1}}{2}} \right)\mspace{11mu}\sin\;\theta}}$${{MS24}\text{:}\mspace{14mu} V_{T24}} = {V_{T} - {{\alpha\left( {W + \frac{L}{2} + \frac{3d_{1}}{2}} \right)}\mspace{11mu}\cos\;\theta} + {\alpha\mspace{11mu}\left( {\frac{W}{2} + \frac{d_{1}}{2}} \right)\mspace{11mu}\sin\;\theta}}$

In the equations described above, d1 denotes a distance between drains(sources) of neighboring sub-transistors, Ws denotes a width of a gateof the sub-transistor and Ls denotes a length of the gate of thesub-transistor.

SUMMARY OF THE INVENTION

The four-segment layout scheme described above can achieve bettermatching performance compared with the centroid layout scheme. However,the four-segment layout scheme has a drawback of requiring a largepattern area.

Thus, a circuit layout configuration of this invention is a layoutconfiguration in which a pair of transistors required close matching isdivided into sub-transistors arrayed in a matrix with four rows and fourcolumns forming four cells each composed of four sub-transistors, andthe sub-transistors belonging to each cell have a common center, asshown in FIG. 1.

This can realize a layout configuration that is as good in matching ofthe pair of transistors as the four-segment layout scheme and takessmall pattern area.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is a plan view showing a multiple-common-centroid layoutconfiguration according to an embodiment of this invention.

FIG. 2 is an equivalent circuit diagram of the multiple-common-centroidlayout configuration according to the embodiment of this invention.

FIG. 3 is a schematic diagram of the multiple-common-centroid layoutconfiguration according to the embodiment of this invention.

FIG. 4 is a circuit diagram of a circuit used for simulations of variouskinds of layout.

FIG. 5 shows results of simulations using HSPICE.

FIG. 6 shows results of simulations using HSPICE.

FIG. 7 is a circuit diagram showing a differential gain stage.

FIG. 8 is a plan view showing a common-centroid layout scheme.

FIG. 9 is an equivalent circuit diagram of the common-centroid layoutscheme.

FIG. 10 a plan view showing a four-segment layout scheme.

FIG. 11 is an equivalent circuit diagram of the four-segment layoutscheme.

DETAILED DESCRIPTION OF THE INVENTION

Next, an embodiment of this invention will be explained in detail,referring to figures. FIG. 1 shows a multiple-common-centroid layoutconfiguration. FIG. 2 shows an equivalent circuit diagram of FIG. 1. M1and M2 are MOS field effect transistors that are to be matched. Thefirst transistor M1, that is a main-transistor, is divided into eightsub-transistors MS11, MS12, MS13, MS14, MS15, MS16, MS17 and MS18.Gates, drains and sources of these sub-transistors are connected incommon to form the first transistor M1.

And similarly, the second transistor M2, that is a main-transistor, isalso divided into eight sub-transistors MS21, MS22, MS23, MS24, MS25,MS26, MS27 and MS28. And gates, drains and sources of thesesub-transistors are connected in common to form the second transistorM2.

The first transistor M1 and the second transistor M2 can formdifferential input pair transistors of a differential amplifier. Andwhen a current mirror is formed with the first transistor M1 and thesecond transistor M2, the gates of the sub-transistors are connected incommon with each other.

Above-mentioned 16 sub-transistors forming the first and secondtransistors M1 and M2 are arrayed in a matrix with four rows and fourcolumns, when viewed as a whole. The matrix is formed of four cells. Afirst cell C1 is composed of the sub-transistors MS11 and MS12 and thesub-transistors MS21 and MS22:

A second cell C2 is composed of the sub-transistors MS13 and MS14 andthe sub-transistors MS23 and MS24. A third cell C3 is composed of thesub-transistors MS15 and MS16 and the sub-transistors MS25 and MS26. Afourth cell C4 is composed of the sub-transistors MS17 and MS18 and thesub-transistors MS27 and MS28.

To explain the first cell C1 in detail, the sub-transistor MS21 disposedat a first row and a first column, the sub-transistor MS22 disposed at asecond row and a second column, the sub-transistor MS11 disposed at thefirst row and the second column and the sub-transistor MS12 disposed atthe second row and the first column have a common center P1.

The sources and drains of these sub-transistors are arrayed parallel toa column direction while their gates are arrayed parallel to a rowdirection. And the second cell C2, the third cell C3 and the fourth cellC4 are formed with symmetrical configuration based on the first cell C1.Each of the second cell C2, the third cell C3 and the fourth cell C4 haseach of common centers P2, P3 and P4, respectively.

FIG. 3 is a layout to explain a concept of the symmetrical configurationclearly. In the figure, the sub-transistors forming the first transistorM1 are marked with “1”, and the sub-transistors forming the secondtransistor M2 are marked with “2”. As seen from the figure, the secondcell C2 is obtained by disposing the first cell C1 axisymmetrically(mirror symmetrically) with respect to a line of symmetry MR1. Also, thethird cell C3 is obtained by disposing the first cell C1axisymmetrically with respect to a line of symmetry MR2. The fourth cellC4 is obtained by disposing the second cell C2 axisymmetrically withrespect to the line of symmetry MR2.

With that, a circuit layout configuration of the first transistor M1 andthe second transistor M2 is obtained. When it is defined as a macro cellMC1, a macro cell MC2 that is axisymmetrical with respect to a line ofsymmetry MR3 is obtained based on the macro cell MC1. And a macro cellMC3 and a macro cell MC4, that are axisymmetrical with respect to a lineof symmetry MR4, can be further obtained based on the macro cells MC1and MC2.

Furthermore, a macro cell that is not shown in the figure can beobtained by disposing the macro cells MC1, MC2, MC3 and MC4 with respectto a line of symmetry MR5. Macro cells can be increased indefinitely byrepeating such symmetrical configuration.

Next, when the threshold voltage model described above is applied to the16 sub-transistors mentioned above, a threshold value for each of thesub-transistors is given by each of the following equations. An originO, a gradient amplitude a and a gradient direction θ are defined in FIG.1.

${{MS11}\text{:}\mspace{14mu} V_{T11}} = {V_{T} + {\alpha\mspace{11mu}\left( {\frac{3W_{S}}{2} + d_{1}} \right)\mspace{11mu}\cos\;\theta} + {\alpha\mspace{11mu}\left( {\frac{7L_{S}}{2} + {2d_{2}} + d_{3}} \right)\mspace{11mu}\sin\;\theta}}$${{MS12}\text{:}\mspace{14mu} V_{T12}} = {V_{T} + {\frac{W_{S}}{2}{\alpha cos\theta}} + {\alpha\mspace{11mu}\left( {\frac{5L_{S}}{2} + d_{2} + d_{3}} \right)\mspace{11mu}\sin\;\theta}}$${{MS13}\text{:}\mspace{14mu} V_{T13}} = {V_{T} + {\alpha\mspace{11mu}\left( {\frac{5W_{S}}{2} + {2d_{1}}} \right)\mspace{11mu}\cos\;\theta} + {\alpha\mspace{11mu}\left( {\frac{7L_{S}}{2} + {2d_{2}} + d_{3}} \right)\mspace{11mu}\sin\;\theta}}$${{MS14}\text{:}\mspace{14mu} V_{T14}} = {V_{T} + {\alpha\mspace{11mu}\left( {\frac{7W_{S}}{2} + {3d_{1}}} \right)\mspace{11mu}\cos\;\theta} + {\alpha\mspace{11mu}\left( {\frac{5L_{S}}{2} + d_{2} + d_{3}} \right)\mspace{11mu}\sin\;\theta}}$${{MS15}\text{:}\mspace{14mu} V_{T15}} = {V_{T} + {\frac{W_{S}}{2}{\alpha cos\theta}} + {\alpha\mspace{11mu}\left( {\frac{3L_{S}}{2} + d_{2}} \right)\mspace{11mu}\sin\;\theta}}$${{MS16}\text{:}\mspace{14mu} V_{T16}} = {V_{T} + {\alpha\mspace{11mu}\left( {\frac{3W_{S}}{2} + d_{1}} \right)\mspace{11mu}\cos\;\theta} + {\frac{L_{S}}{2}{\alpha sin\theta}}}$${{MS17}\text{:}\mspace{14mu} V_{T17}} = {V_{T} + {\alpha\mspace{11mu}\left( {\frac{7W_{S}}{2} + {3d_{1}}} \right)\mspace{11mu}\cos\;\theta} + {\alpha\mspace{11mu}\left( {\frac{3L_{S}}{2} + d_{2}} \right)\mspace{11mu}\sin\;\theta}}$${{MS18}\text{:}\mspace{14mu} V_{T18}} = {V_{T} + {\alpha\mspace{11mu}\left( {\frac{5W_{S}}{2} + {2d_{1}}} \right)\mspace{11mu}\cos\;\theta} + {\frac{L_{S}}{2}{\alpha sin\theta}}}$${{MS21}\text{:}\mspace{14mu} V_{T21}} = {V_{T} + {\frac{W_{S}}{2}{\alpha cos\theta}} + {\alpha\mspace{11mu}\left( {\frac{7L_{S}}{2} + {2d_{2}} + d_{3}} \right)\mspace{11mu}\sin\;\theta}}$${{MS22}\text{:}\mspace{14mu} V_{T22}} = {V_{T} + {{\alpha\left( {\frac{3W_{S}}{2} + d_{1}} \right)}\mspace{11mu}\cos\;\theta} + {\alpha\mspace{11mu}\left( {\frac{5L_{S}}{2} + d_{2} + d_{3}} \right)\mspace{11mu}\sin\;\theta}}$${{MS23}\text{:}\mspace{14mu} V_{T23}} = {V_{T} + {\alpha\mspace{11mu}\left( {\frac{7W_{S}}{2} + {3d_{1}}} \right)\mspace{11mu}\cos\;\theta} + {\alpha\mspace{11mu}\left( {\frac{7L_{S}}{2} + {2d_{2}} + d_{3}} \right)\mspace{11mu}\sin\;\theta}}$${{MS24}\text{:}\mspace{14mu} V_{T24}} = {V_{T} + {\alpha\mspace{11mu}\left( {\frac{5W_{S}}{2} + {2d_{1}}} \right)\mspace{11mu}\cos\;\theta} + {\alpha\mspace{11mu}\left( {\frac{5L_{S}}{2} + d_{2} + d_{3}} \right)\mspace{11mu}\sin\;\theta}}$${{MS25}\text{:}\mspace{14mu} V_{T25}} = {V_{T} + {\alpha\mspace{11mu}\left( {\frac{3W_{S}}{2} + d_{1}} \right)\mspace{11mu}\cos\;\theta} + {\alpha\mspace{11mu}\left( {\frac{3L_{S}}{2} + d_{2}} \right)\mspace{11mu}\sin\;\theta}}$${{MS26}\text{:}\mspace{14mu} V_{T26}} = {V_{T} + {\frac{W_{S}}{2}{\alpha cos\theta}} + {\frac{L_{S}}{2}{\alpha sin}\;\theta}}$${{MS27}\text{:}\mspace{14mu} V_{T27}} = {V_{T} + {\alpha\mspace{14mu}\left( {\frac{5W_{S}}{2} + {2d_{1}}} \right)\mspace{11mu}\cos\;\theta} + {\alpha\mspace{11mu}\left( {\frac{3L_{S}}{2} + d_{2}} \right)\mspace{11mu}\sin\;\theta}}$${{MS28}\text{:}\mspace{14mu} V_{T28}} = {V_{T} + {\alpha\mspace{11mu}\left( {\frac{7W_{S}}{2} + {3d_{1}}} \right)\mspace{11mu}\cos\;\theta} + {\frac{L_{S}}{2}\;{\alpha sin}\;\theta}}$

In the equations described above, d1 denotes a distance between drains(sources) of neighboring sub-transistors, d2 and d3 denote distancesbetween gates of neighboring sub-transistors, Ws denotes a width of thegate of the sub-transistor and Ls denotes a length of the gate of thesub-transistor.

Next, simulations using HSPICE are explained. An aim of the simulationsis to check performance of various transistor-matching layouts withrespect to change in the gradient direction θ. Parameters common to allthe simulations are, d1=d2=d3 4 μm, α=0.5 mV/μm, V_(T)=0.7V

FIG. 4 shows a circuit diagram of a circuit used for the simulations. Afirst transistor M1, that is a main-transistor, is divided into Nsub-transistors MS11-MS1N, and a bias voltage V_(B) is applied to theirgates in common. And a high power supply Vdd is applied to a commondrain D1 of the sub-transistors MS11-MS1N through a resistor R. And alow power supply Vss is applied to a common source S1 of thesub-transistors MS11-MS1N.

A second transistor M2, that is a main-transistor, is divided into Nsub-transistors MS21-MS2N, and a bias voltage V_(B) is applied to theirgates in common. And the high power supply Vdd is applied to a commondrain D2 of the sub-transistors MS21-MS2N through a resistor R. And thelow power supply Vss is applied to a common source S2 of thesub-transistors MS21-MS2N.

Here, for all the simulations performed, a percent mismatch is definedby the following equation.

${{Percent}\mspace{14mu}{Mismatch}} = {\frac{I_{M2} - I_{M1}}{I_{M1}} \times 100}$

Here, I_(M1) denotes a current flowing through the first transistor M1and I_(M2) denotes a current flowing through the second transistor M2.Two sets of simulations are performed to compare the performance of thedifferent transistor-matching layouts. In a first set, sizes of thesub-transistors are set as Ws=10 μm and Ls=10 μm for all the layoutschemes.

Thus, widths W and lengths L for various layout schemes are as follows.

common-centroid layout: W = 20 μm L = 10 μm four-segment layout: W = 40μm L = 10 μm multiple-common-centroid layout: W = 80 μm L = 10 μm

FIG. 5 shows simulation results for the first set of simulations. Ahorizontal axis shows the gradient direction θ, while a vertical axisshows the percent mismatch (%). As clearly seen from the results, themultiple-common-centroid layout of this invention shows an improvementin the matching performance comparable to the common-centroid layout.That is, the percent mismatch (%) for the multiple-common-centroidlayout is three orders smaller than that for the common-centroid layout.

A second set of the simulation is performed under conditions that sizesof the first transistor M1 and the second transistor M2 are same for allthe layout schemes. That is, the width W is 80 μm and the length W is 10μm for the first transistor M1 and for the second transistor M2. Thus,dimensions of the sub-transistors for various layout schemes are asfollows.

common-centroid layout: Ws = 40 μm Ls = 10 μm four-segment layout: Ws =20 μm Ls = 10 μm multiple-common-centroid layout: Ws = 10 μm Ls = 10 μm

FIG. 6 shows simulation results for the second set of simulations. Ahorizontal axis shows the gradient direction θ, while a vertical axisshows the percent mismatch (%). The percent mismatch (%) for themultiple-common-centroid layout of this invention is improved comparedwith either of the other layouts, as the results clearly show.

Also, the multiple-common-centroid layout of this invention has afeature that it takes less layout area compared with the four-segmentlayout. Effect of the improvement in the matching by themultiple-common-centroid layout can be achieved at slightly more layoutarea requirement compared to the common-centroid layout.

The table below shows formulae to calculate areas for three differentlayout schemes and the calculated areas for a given set of parameters.Dimensions of the first transistor M1 and the second transistor M2, thatare main-transistors, are the width W=80 μm and the length W=10 μm withd1=d2=d3=4 μm for all the layout schemes.

For the common-centroid layout, each of the main-transistors is dividedinto two sub-transistors. The width Ws is 40 μm and the length Ls is 10μm for each of the sub-transistors. For the four-segment layout, each ofthe main-transistors is divided into four sub-transistors. The width Wsis 20 μm and the length Ls is 10 μm for each of the sub-transistors.

For the multiple-common-centroid layout of this invention, each of themain-transistors is divided into eight sub-transistors. The width Ws is10 μm and the length Ls is 10 μm for each of the sub-transistors.

TABLE Calculated Area* [W = 80□m, L = 10□m Layout Type Area EstimationFormulae* d1 = d2 = d3 = 4□m] Common-Centroid (2L_(s) + d₂)(2W_(s) + d₁)2.016e − 9m² [W_(s) = 40□, L_(s) = 10□] Four-Segmented (2W_(s) +2L_(s) + 3d₁)(2W_(s) + 2L_(s) + 3d₁) 5.184e − 9m² [W_(s) = 20□, L_(s) =10□] Multiple-Common-Cent- (4L_(s) + 2d₂ + d₃)(4W_(s) + 3d₁) 2.704e −9m² roid [W_(s) = 10□, L_(s) = 10□] *L_(s) and W_(s) represent thedimensions of the sub-transistors. *L and W represent the dimensions ofthe main-transistors.

As described above, the multiple-common-centroid layout of thisinvention has the effect that the matching performance comparable to thefour-segment layout can be obtained while the layout area can be madesmall.

In particular, a low offset operational amplifier can be realized byapplying the layout of this invention to a differential transistor pairand a transistor pair forming a current mirror of the operationalamplifier.

1. A circuit layout configuration for matching two transistors,comprising: a first transistor comprising eight first sub-transistors;and a second transistor comprising eight second sub-transistors, whereinthe eight first sub-transistors and the eight second sub-transistors arearranged in a four by four matrix, the eight second sub-transistorsoccupy eight diagonal positions of the four by four matrix, and theeight first sub-transistors occupy positions of the four by four matrixthat are not the diagonal positions.
 2. The circuit layout configurationof claim 1, wherein gates of the eight first sub-transistor and theeight second sub-transistors are connected so that the first transistorand the second transistor form a current mirror circuit.
 3. The circuitlayout configuration of claim 1, wherein gates of the firstsub-transistors are connected to form a gate of the first transistor andgates of the second sub-transistors are connected to form a gate of thesecond transistor.
 4. The circuit layout configuration of claim 3,wherein the first and second transistors form differential input pairtransistors of an operational amplifier.
 5. The circuit layoutconfiguration of claim 1, wherein sources of the first sub-transistorsare connected and drains of the first sub-transistors are connected. 6.The circuit layout configuration of claim 5, wherein sources of thesecond sub-transistors are connected and drains of the secondsub-transistors are connected.
 7. The circuit layout configuration ofclaim 1 wherein the first transistor comprises eight additional firstsub-transistors, the second transistor comprises eight additional secondsub-transistors, and the eight additional first sub-transistors and theeight additional second sub-transistors are arranged so as to besymmetrical with the eight first sub-transistors and the eight secondsub-transistors with respect to a line of symmetry.